1. Field of the Invention
The present invention is related to a shift register, and more particularly, to a shift register which improves the ability of pulling down the voltage level of the output node of the shift register.
2. Description of the Prior Art
The gate driver of a LCD device utilizes shift register for generating sequential scan signals. Conventionally the shift register is manufactured onto the glass substrate of the LCD device by amorphous silicon thin film transistors (a-Si TFTs) and low temperature polycrystalline silicon (LTPS) TFTs processes. The shift register usually includes multistage circuits, so certain TFTs are turned on for a relative long period of time. However, when the voltage is continuously and frequently applied to the TFTs or the LTPS TFTs for a long period of time, the TFTs tend to become malfunction due to degradation, consequently the reliability of the shift register is sabotaged.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating the conventional shift register. In the Nth shift register 100, the first transistor Q1 is utilized to drive the second transistor Q2. The control end and the first end of the first transistor Q1 are electrically connected to the input end of the shift register, for receiving the output signal of the previous stage SR(N−1). The second end of the first transistor Q1 is electrically connected to the control end of the second transistor Q2. The first end of the second transistor Q2 is utilized to receive the first signal CK1. The second end of the second transistor Q2 is electrically connected to the output end OUT of the shift register, for outputting the first signal CK1 to the output end OUT according to the voltage level of the driving node G. The shift register 100 includes a first pull-down module 110 and a second pull-down module 120. The third transistor Q3 and the ninth transistor Q9 are electrically connected to the output end OUT, for pulling the voltage level of the output end OUT to a low voltage level VSS after the output end OUT outputs a high level voltage. The sixth transistor Q6 and the tenth transistor Q10 are electrically connected to the driving node G, for pulling the voltage level of the driving node G to the low voltage level VSS to turn off the second transistor Q2, after the output end OUT outputs the high voltage level. The first pull-down module 110 and the second pull-down module 120 each approximately execute the pull down operation 50% of the time, according to the first signal CK1 and the second signal CK2 respectively. In the first pull-down module 110, the control ends of the ninth transistor Q9 and the tenth transistor Q10 are electrically connected to the node K. The voltage level of the node K is determined by the twelfth transistor Q12 and the thirteenth transistor Q13. In the second pull-down module 120, the control ends of the third transistor Q3 and the sixth transistor Q6 are electrically connected to the node P. The voltage level of the node P is determined by the fourth transistor Q4 and the fifth transistor Q5. The eleventh transistor Q11 is utilized to pull the voltage level of the node K to the low voltage level VSS. The seventh transistor Q7 is utilized to pull the voltage level of the node P to the low voltage level VSS when the output end OUT outputs the high voltage level. Furthermore, the eighth transistor Q8 is electrically connected to the node P, for pulling the voltage level of the node P to the low voltage level VSS when the output end OUT outputs the high voltage level.
The second signal CK2 is complementary to the first signal CK1; when the first signal CK1 is of the high voltage level and the second signal CK2 is of the low voltage level VSS, the voltage level of the node P is of the low voltage level VSS and the voltage level of the node K is of the high voltage level. However, the voltage level of the node K is pulled to the low voltage level VSS by the eleventh transistor Q11 except when the output end OUT outputs the high voltage level. Similarly, when the first signal CK1 is of the low voltage level VSS and the second signal CK2 is of the high voltage level, the voltage level of the node K is of the low voltage level VSS and the voltage level of the node P is of the high voltage level. However, the voltage level of the node P is pulled to the low voltage level VSS by the seventh transistor Q7 and the eighth transistor Q8 except when the output end OUT outputs the high voltage level.
The voltage level of the nodes K and P are maintained at the high voltage level approximately 50% of the time, and at the low voltage level VSS for the other 50% of the time. When at the high voltage level, the transistor is turned on and the threshold value of the transistor accordingly increases; when at the low voltage level, the threshold value of the transistor decreases. When the high voltage level is of an inverted value to the low voltage level, the increased magnitude of the threshold value is equivalent to the decreased magnitude of the threshold value; the net variation of the threshold value is approximately zero and the operation of the shift register is then considered as stable. However, the current conventional high voltage level is around +18V and the low voltage level VSS is around −6V. Therefore, the variation of the threshold values of the third transistor Q3, the sixth transistor Q6, the ninth transistor Q9 and the tenth transistor 10 controlled by the nodes K and P increases with time, causing the shift register to be unstable.